 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HV62106 64-Channel Gray-Shade Display Column Driver Ordering Information Package Options* Device HV62106 Die in wafer form HV62106XW Die in waffle pack HV62106X *Consult factory for availability of bumped die. Features 5V CMOS inputs 64 outputs per device Up to 60V output voltage Capable of 4 output pulse widths PWM gray shade conversion Two 2-bit data buses 28 MHz data throughput rate Pin-programmable shift direction (DIR) Integrated high-voltage CMOS technology Optimized layout for COG use General Description Not recommended for new designs. The HV62106 is a 64-channel column driver IC designed for gray shade flat panel displays. Using Supertex's unique HVCMOS(R) technology, it is capable of providing gray shading by pulse width modulation (PWM) conversion. A high level on the chip select input enables the IC to load data into a set of input data latches. This input data, in two groups of two, are latched into the input data latches on both edges of the Shift Clock. The data stored in these input data latches is transferred to a set of output data latches on the rising edge of Load Count. After the input data registers are full, a chip select output signal is provided for enabling the next IC in the chain. A master binary counter is reset with a high level on Load Count and is incremented on the rising edge of Count Clock. The data stored in the output data latches is compared to the contents of the master counter. The output of the comparator drives the high voltage output devices. The higher the binary number in the output data latches, the longer the pulse width will be on the corresponding output. DIR is a shift-direction-select input which is provided to interchange the direction of the latched data inputs. When the DIR input is high, CS2 becomes chip select input and data is latched into the data latches in the sequence of HVOUT1 to HVOUT64. When the DIR input is low, CS1 becomes chip select input and data is latched into the data latches in the sequence of HVOUT64 to HVOUT1. DIN1 and DIN2 load in data for odd number of outputs. DIN3 and DIN4 load in data for even number of outputs. 12 Absolute Maximum Ratings Supply voltage, VDD Supply voltage, VPP Logic input levels Operating temperature range Storage temperature range Note: All voltages are referenced to GND. -0.5V to +7.5V -0.5V to +70V -0.5V to VDD + 0.5V -40C to +85C -65C to +150C 12-111 HV62106 Electrical Characteristics (Over recommended conditions of VDD = 5V, VPP = 60V, TA = 25C unless otherwise noted) Low Voltage DC Characteristics Symbol IDD IDDQ IIH IIL IOH IOL Parameter VDD supply current Quiescent VDD supply current High-level input current Low-level input current High-level output current Low-level output current -1 1 Min Max 10 1 10 -10 Units mA mA A A mA mA Conditions fSC = 7MHz, fCC = 3MHz All VIN = GND VIH = VDD VIL = GND High Voltage DC Characteristics Symbol IPPQ VOH VOL Parameter Quiescent VPP supply current High-level output Low-level output 50 8 Min Max 100 Units A V V Conditions All HVOUT low or high IOUT = -12mA IOUT = 15mA AC Characteristics (Logic Timing) Symbol fSC fDIN fCC tWA tSS tHS tDS tDH tWLC tDLCC tDSL tCSC tDLC tWCC tCCC tDCC tWSC tWD Parameter Shift clock frequency Data In frequency Count clock frequency Chip select pulse width Chip select set-up time Chip select hold time Data to shift clock set-up time Data to shift clock hold time Load count pulse width Load count to count clock delay Shift clock to load count delay Shift clock cycle time Load count to HVOUT delay Count clock pulse width Count clock cycle time Count clock to HVOUT delay Shift clock pulse width Data in pulse width 70 60 160 333 1.5 80 20 40 -10 30 160 70 200 143 1.5 30 Min Max 7 7 3 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns s ns ns s ns ns CL = 15pF // RL = 10M CL = 15pF // RL = 10M Conditions 12-112 HV62106 Recommended Operating Conditions Symbol VPP VDD VIL VIH fSC fCC TA Parameter High voltage supply Logic supply voltage Low-level input voltage High-level input voltage Shift clock frequency Count clock frequency Operating temperature -40 Min 0 4.5 0 VDD-1 Max 60 5.5 1 VDD 7 3 +85 Units V V V V MHz MHz C Conditions Pad Definitions Pad # 2-5 18 -21 23, 33 24, 32 10, 22 8, 15 26, 30 27, 29 14, 28 1, 41 42-105 25, 31 6, 17 7, 16 Name DIN1 - DIN4 Shift Clock CS1 CS2 Load Count DIR GND HVGND VPP HVOUT1 - 64 VDD Count Clock (GCLK) Count Clock (RCLK) I/O I I I/O I/O I I -- -- -- O -- I I Function Inputs for binary-format parallel data (DIN2 and DIN4 are the most significant bits) Latching data on both edges Input when DIR = 0; Output when DIR = 1 Output when DIR = 0; Input when DIR = 1 Initiates the conversion Controls the data shift directions Logic ground High voltage ground High voltage supply High voltage outputs Logic supply voltage Input for incrementing the master counter for the green pixel Input for incrementing the master counter for the red pixel Function Table Sequence 1 2 3 4 Function Load data from data bus Load counter Counting/conversion Next cycle Data-In (D1 - D4) H/L X X H/L CS1/ CS2 CS2/ CS1 X X X X Shift Clock Load Count L Count Clock (RCLK, GCLK) H H L L H H/L L HVOUT L L L X X 12-113 HV62106 Functional Block Diagram DIN (3, 4) DIN (1, 2) VPP 2 Data 2 2 CS2 2 > Data Latch > Latch Comparator 2 Logic L/T HVOUT1 HVOUT3 HVOUT5 > Data Latch DIR 2 * * * > Latch Data 2 Comparator Logic L/T > > Data Latch HVOUT2 HVOUT4 HVOUT6 2 2 Data 2 Logic L/T * * * > Latch Comparator 2 HVOUT63 > Data Latch Shift Clock 2 > Latch CS1 Load Count Data 2 Comparator Logic L/T HVOUT64 > Count Clock (GCLK, RCLK) L/T = Level Translator Input and Output Equivalent Circuits VDD VDD VPP Input Data Out HVOUT GND Logic Inputs GND Logic Data Output HVGND High Voltage Outputs 12-114 HV62106 Timing Diagrams tWA CS1/2 tSS Shift Clock tHS 1 2 3 16 1 2 50% Current Loading Cycle Next Loading Cycle Data In SET 1 SET 2 SET 3 SET 4 SET 5 SET 30 SET 31 SET 32 SET 1 SET 2 tCSC Shift Clock 16 1 2 tWSC tDS tDH Data In SET 30 SET 31 tWD SET 32 SET 1 SET 2 SET 3 CS2/1 Current Loading Cycle Next Loading Cycle Shift Clock tWLC tDSL Count Clock (RCLK, GCLK) tDLCC tWCC 50% tCCC tDLC 50% 50% 10% Load Count 50% 50% 50% 90% HVOUT tDCC 12-115 |
Price & Availability of HV62106XW
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |